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pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW

This change does the following:
- Removes the printing of the PCI interrupt line value.  This is
  normally set to 0 by U-Boot on bootup and is rarely used during
  everyday operation.

- Prints out the PCI function number of a device.  Previously a device
  with multiple functions would be printed identically 2 times, which is
  generally confusing.  For example, on an Intel 2 port gigabit Ethernet
  card the following was displayed:
    ...
    04  01  8086  1010  0200  00
    04  01  8086  1010  0200  00
    ...

- Prints a text description of each device's PCI class instead of the
  raw PCI class code.  The textual description makes it much easier to
  determine what devices are installed on a PCI bus.

- Changes the general formatting of the PCI device output.

Previous output:
  PCIE1: connected as Root Complex
          04  01  8086  1010  0200  00
          04  01  8086  1010  0200  00
          03  00  10b5  8112  0604  00
          02  01  10b5  8518  0604  00
          02  02  10b5  8518  0604  00
          08  00  1957  0040  0b20  00
          07  00  10b5  8518  0604  00
          09  00  10b5  8112  0604  00
          07  01  10b5  8518  0604  00
          07  02  10b5  8518  0604  00
          06  00  10b5  8518  0604  00
          02  03  10b5  8518  0604  00
          01  00  10b5  8518  0604  00
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
          0d  00  1957  0040  0b20  00
  PCIE2: Bus 0c - 0d

Updated output:
  PCIE1: connected as Root Complex
          04:01.0 - 8086:1010 - Network controller
          04:01.1 - 8086:1010 - Network controller
          03:00.0 - 10b5:8112 - Bridge device
          02:01.0 - 10b5:8518 - Bridge device
          02:02.0 - 10b5:8518 - Bridge device
          08:00.0 - 1957:0040 - Processor
          07:00.0 - 10b5:8518 - Bridge device
          09:00.0 - 10b5:8112 - Bridge device
          07:01.0 - 10b5:8518 - Bridge device
          07:02.0 - 10b5:8518 - Bridge device
          06:00.0 - 10b5:8518 - Bridge device
          02:03.0 - 10b5:8518 - Bridge device
          01:00.0 - 10b5:8518 - Bridge device
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
          0d:00.0 - 1957:0040 - Processor
  PCIE2: Bus 0c - 0d

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
master
Peter Tyser 10 years ago
committed by Wolfgang Denk
parent
commit
983eb9d162
3 changed files with 92 additions and 92 deletions
  1. +2
    -64
      common/cmd_pci.c
  2. +89
    -28
      drivers/pci/pci.c
  3. +1
    -0
      include/pci.h

+ 2
- 64
common/cmd_pci.c View File

@ -104,68 +104,6 @@ void pciinfo(int BusNum, int ShortPCIListing)
}
}
static char *pci_classes_str(u8 class)
{
switch (class) {
case PCI_CLASS_NOT_DEFINED:
return "Build before PCI Rev2.0";
break;
case PCI_BASE_CLASS_STORAGE:
return "Mass storage controller";
break;
case PCI_BASE_CLASS_NETWORK:
return "Network controller";
break;
case PCI_BASE_CLASS_DISPLAY:
return "Display controller";
break;
case PCI_BASE_CLASS_MULTIMEDIA:
return "Multimedia device";
break;
case PCI_BASE_CLASS_MEMORY:
return "Memory controller";
break;
case PCI_BASE_CLASS_BRIDGE:
return "Bridge device";
break;
case PCI_BASE_CLASS_COMMUNICATION:
return "Simple comm. controller";
break;
case PCI_BASE_CLASS_SYSTEM:
return "Base system peripheral";
break;
case PCI_BASE_CLASS_INPUT:
return "Input device";
break;
case PCI_BASE_CLASS_DOCKING:
return "Docking station";
break;
case PCI_BASE_CLASS_PROCESSOR:
return "Processor";
break;
case PCI_BASE_CLASS_SERIAL:
return "Serial bus controller";
break;
case PCI_BASE_CLASS_INTELLIGENT:
return "Intelligent controller";
break;
case PCI_BASE_CLASS_SATELLITE:
return "Satellite controller";
break;
case PCI_BASE_CLASS_CRYPT:
return "Cryptographic device";
break;
case PCI_BASE_CLASS_SIGNAL_PROCESSING:
return "DSP";
break;
case PCI_CLASS_OTHERS:
return "Does not fit any class";
break;
default:
return "???";
break;
};
}
/*
* Subroutine: pci_header_show_brief
@ -190,7 +128,7 @@ void pci_header_show_brief(pci_dev_t dev)
printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
vendor, device,
pci_classes_str(class), subclass);
pci_class_str(class), subclass);
}
/*
@ -225,7 +163,7 @@ void pci_header_show(pci_dev_t dev)
PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
pci_classes_str);
pci_class_str);
PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);


+ 89
- 28
drivers/pci/pci.c View File

@ -510,6 +510,71 @@ void pci_cfgfunc_do_nothing(struct pci_controller *hose,
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern void pciauto_config_init(struct pci_controller *hose);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
const char * pci_class_str(u8 class)
{
switch (class) {
case PCI_CLASS_NOT_DEFINED:
return "Build before PCI Rev2.0";
break;
case PCI_BASE_CLASS_STORAGE:
return "Mass storage controller";
break;
case PCI_BASE_CLASS_NETWORK:
return "Network controller";
break;
case PCI_BASE_CLASS_DISPLAY:
return "Display controller";
break;
case PCI_BASE_CLASS_MULTIMEDIA:
return "Multimedia device";
break;
case PCI_BASE_CLASS_MEMORY:
return "Memory controller";
break;
case PCI_BASE_CLASS_BRIDGE:
return "Bridge device";
break;
case PCI_BASE_CLASS_COMMUNICATION:
return "Simple comm. controller";
break;
case PCI_BASE_CLASS_SYSTEM:
return "Base system peripheral";
break;
case PCI_BASE_CLASS_INPUT:
return "Input device";
break;
case PCI_BASE_CLASS_DOCKING:
return "Docking station";
break;
case PCI_BASE_CLASS_PROCESSOR:
return "Processor";
break;
case PCI_BASE_CLASS_SERIAL:
return "Serial bus controller";
break;
case PCI_BASE_CLASS_INTELLIGENT:
return "Intelligent controller";
break;
case PCI_BASE_CLASS_SATELLITE:
return "Satellite controller";
break;
case PCI_BASE_CLASS_CRYPT:
return "Cryptographic device";
break;
case PCI_BASE_CLASS_SIGNAL_PROCESSING:
return "DSP";
break;
case PCI_CLASS_OTHERS:
return "Does not fit any class";
break;
default:
return "???";
break;
};
}
#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
@ -568,44 +633,40 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
if (vendor != 0xffff && vendor != 0x0000) {
if (vendor == 0xffff || vendor == 0x0000)
continue;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
sub_bus = max(sub_bus, hose->current_busno);
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
sub_bus = max(sub_bus, hose->current_busno);
#ifdef CONFIG_PCI_PNP
} else {
int n = pciauto_config_device(hose, dev);
} else {
int n = pciauto_config_device(hose, dev);
sub_bus = max(sub_bus, n);
sub_bus = max(sub_bus, n);
#endif
}
if (hose->fixup_irq)
hose->fixup_irq(hose, dev);
}
if (hose->fixup_irq)
hose->fixup_irq(hose, dev);
#ifdef CONFIG_PCI_SCAN_SHOW
if (pci_print_dev(hose, dev)) {
unsigned char int_line;
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
&int_line);
printf(" %02x %02x %04x %04x %04x %02x\n",
PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
int_line);
}
#endif
if (pci_print_dev(hose, dev)) {
printf(" %02x:%02x.%x - %04x:%04x - %s\n",
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev),
vendor, device, pci_class_str(class >> 8));
}
#endif
}
return sub_bus;


+ 1
- 0
include/pci.h View File

@ -536,6 +536,7 @@ extern int pci_hose_config_device(struct pci_controller *hose,
pci_addr_t mem,
unsigned long command);
const char * pci_class_str(u8 class);
int pci_last_busno(void);
#ifdef CONFIG_MPC824X


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