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MLK-16238-3 imx8m_evk: Update codes to enable TMU

Update SoC codes, DTSi and defconfig to enable TMU for i.MX8M EVK board.
Also implement functions to get speed grade and market segment info from fuse.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 3150830e67)
Ye Li 3 years ago
parent
commit
946c65698a
5 changed files with 95 additions and 0 deletions
  1. +2
    -0
      arch/arm/cpu/armv8/imx8m/clock.c
  2. +78
    -0
      arch/arm/cpu/armv8/imx8m/soc.c
  3. +1
    -0
      arch/arm/dts/fsl-imx8mq.dtsi
  4. +11
    -0
      arch/arm/include/asm/arch-imx8m/imx-regs.h
  5. +3
    -0
      configs/imx8mq_evk_defconfig

+ 2
- 0
arch/arm/cpu/armv8/imx8m/clock.c View File

@ -590,6 +590,8 @@ int clock_init()
clock_enable(CCGR_WDOG2, 1);
clock_enable(CCGR_WDOG3, 1);
clock_enable(CCGR_TSENSOR, 1);
return 0;
};


+ 78
- 0
arch/arm/cpu/armv8/imx8m/soc.c View File

@ -15,6 +15,84 @@
DECLARE_GLOBAL_DATA_PTR;
/*
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
*/
#define OCOTP_TESTER3_SPEED_SHIFT 8
#define OCOTP_TESTER3_SPEED_800MHZ 0
#define OCOTP_TESTER3_SPEED_1GHZ 1
#define OCOTP_TESTER3_SPEED_1300HZ 2
#define OCOTP_TESTER3_SPEED_1500HZ 3
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
uint32_t val;
val = readl(&fuse->tester3);
val >>= OCOTP_TESTER3_SPEED_SHIFT;
val &= 0x3;
switch(val) {
case OCOTP_TESTER3_SPEED_800MHZ:
return 792000000;
case OCOTP_TESTER3_SPEED_1GHZ:
return 996000000;
case OCOTP_TESTER3_SPEED_1300HZ:
return 1300000000;
case OCOTP_TESTER3_SPEED_1500HZ:
return 1500000000;
}
return 0;
}
/*
* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
*/
#define OCOTP_TESTER3_TEMP_SHIFT 6
/* CPU Temperature Grades */
#define TEMP_COMMERCIAL 0
#define TEMP_EXTCOMMERCIAL 1
#define TEMP_INDUSTRIAL 2
#define TEMP_AUTOMOTIVE 3
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
uint32_t val;
val = readl(&fuse->tester3);
val >>= OCOTP_TESTER3_TEMP_SHIFT;
val &= 0x3;
if (minc && maxc) {
if (val == TEMP_AUTOMOTIVE) {
*minc = -40;
*maxc = 125;
} else if (val == TEMP_INDUSTRIAL) {
*minc = -40;
*maxc = 105;
} else if (val == TEMP_EXTCOMMERCIAL) {
*minc = -20;
*maxc = 105;
} else {
*minc = 0;
*maxc = 95;
}
}
return val;
}
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD


+ 1
- 0
arch/arm/dts/fsl-imx8mq.dtsi View File

@ -224,6 +224,7 @@
reg = <0x0 0x30260000 0x0 0x10000>;
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
u-boot,dm-pre-reloc;
fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
fsl,tmu-calibration = <0x00000000 0x00000020
0x00000001 0x00000028


+ 11
- 0
arch/arm/include/asm/arch-imx8m/imx-regs.h View File

@ -192,6 +192,17 @@ struct ocotp_regs {
} bank[0];
};
struct fuse_bank1_regs {
u32 tester3;
u32 rsvd0[3];
u32 tester4;
u32 rsvd1[3];
u32 tester5;
u32 rsvd2[3];
u32 cfg0;
u32 rsvd3[3];
};
struct fuse_bank9_regs {
u32 mac_addr0;
u32 rsvd0[3];


+ 3
- 0
configs/imx8mq_evk_defconfig View File

@ -28,3 +28,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_ETH=y
CONFIG_CMD_PMIC=y
CONFIG_NXP_TMU=y
CONFIG_DM_THERMAL=y

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