Commit 6ad81731 by Jose Miquel Sanabria

IGEP0046: SPL and UBOOT Test

it was created the following source files in board/isee/common: igep_test.c and igep_test.h it was CLEARED igep board folders that do not belong to u-boot-imx like igep00x0 and igep0030 Signed-off-by: Jose Miquel Sanabria's avatarJose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
parent c67aadf4
...@@ -1245,7 +1245,6 @@ source "board/gumstix/pepper/Kconfig" ...@@ -1245,7 +1245,6 @@ source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig" source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig" source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig" source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig" source "board/phytec/pcm052/Kconfig"
......
...@@ -31,12 +31,6 @@ config TARGET_DEVKIT8000 ...@@ -31,12 +31,6 @@ config TARGET_DEVKIT8000
config TARGET_OMAP3_EVM config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM" bool "TI OMAP3 EVM"
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_OMAP3_OVERO config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo" bool "OMAP35xx Gumstix Overo"
select DM select DM
...@@ -105,7 +99,6 @@ source "board/compulab/cm_t35/Kconfig" ...@@ -105,7 +99,6 @@ source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig" source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig" source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig" source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig" source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig" source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig" source "board/ti/am3517crane/Kconfig"
......
#
# Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
#
# Source file for IGEP0046 board
#
# Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SYS_I2C) += igep_eeprom.o
obj-$(CONFIG_SYS_I2C) += igep_test.o
...@@ -13,15 +13,18 @@ ...@@ -13,15 +13,18 @@
#define IGEP_MAGIC_ID 0x6D6A6DE4 #define IGEP_MAGIC_ID 0x6D6A6DE4
/* BOARD UUID INFO TEST STRUCT */
struct __attribute__((packed)) igep_mf_setup { struct __attribute__((packed)) igep_mf_setup {
u32 magic_id; /* eeprom magic id */ u32 magic_id; /* eeprom magic id */
u32 crc32; /* eeprom crc32 */ u32 crc32; /* eeprom crc32 */
char board_uuid [36]; /* board identifier */ char board_uuid [36]; /* board identifier */
char board_pid [16]; /* product identifier */ char board_pid [16]; /* product identifier */
char model [8]; /* board model */ char model [8]; /* board model */
char variant [9]; /* board version */ char variant [9]; /* board version */
char manf_of[6]; /* manufacturer order of fabrication */ char manf_of[6]; /* manufacturer order of fabrication */
char manf_timestamp[19]; /* manufacturer timestamp */ char manf_timestamp[19]; /* manufacturer timestamp */
uchar bmac0[17]; /* MAC 0 - default */ uchar bmac0[17]; /* MAC 0 - default */
uchar bmac1[17]; /* MAC 1 */ uchar bmac1[17]; /* MAC 1 */
}; };
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* *
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com> * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <common.h> #include <common.h>
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size) int eeprom_write_setup (uint16_t s_addr, const char* data, u32 size)
{ {
u32 i; u32 i;
u32 remain = size % 32; u32 remain = size % 32;
...@@ -22,18 +22,18 @@ int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size) ...@@ -22,18 +22,18 @@ int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size)
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){ if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1; return -1;
} }
udelay(5000); mdelay(10);
} }
if(remain > 0){ if(remain > 0){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain)) if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1; return -1;
else else
udelay(5000); mdelay(10);
} }
return 0; return 0;
} }
int eeprom_read_setup (uint8_t s_addr, char* data, u32 size) int eeprom_read_setup (uint16_t s_addr, char* data, u32 size)
{ {
u32 i; u32 i;
u32 remain = size % 32; u32 remain = size % 32;
...@@ -53,10 +53,19 @@ int check_eeprom (void) ...@@ -53,10 +53,19 @@ int check_eeprom (void)
{ {
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
/* Check if baseboard eeprom is available */ /* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
printf("Could not probe the EEPROM at 0x%x\n", printf("Could not probe the EEPROM at 0x%x\n",
CONFIG_SYS_I2C_EEPROM_ADDR); CONFIG_SYS_I2C_EEPROM_ADDR);
return -1; return -1;
} }
return 0; return 0;
} }
unsigned int parse_char(char c)
{
if ('0' <= c && c <= '9') return c - '0';
if ('a' <= c && c <= 'f') return 10 + c - 'a';
if ('A' <= c && c <= 'F') return 10 + c - 'A';
return 0;
}
\ No newline at end of file
...@@ -11,7 +11,8 @@ ...@@ -11,7 +11,8 @@
#ifndef __EEPROM_BOARD_HELPER__ #ifndef __EEPROM_BOARD_HELPER__
#define __EEPROM_BOARD_HELPER__ #define __EEPROM_BOARD_HELPER__
int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size); int eeprom_write_setup (uint16_t s_addr, const char* data, u32 size);
int eeprom_read_setup (uint8_t s_addr, char* data, u32 size); int eeprom_read_setup (uint16_t s_addr, char* data, u32 size);
int check_eeprom (void); int check_eeprom (void);
unsigned int parse_char(char c);
#endif #endif
/* Header file for Test Functions to help header code */
#ifndef __TEST_HEADER__
#define __TEST_HEADER__
/* Magics that are involved */
#define SPL_MAGIC_ID 0xdadd
#define UB_MAGIC_ID 0xbebb
#define SPL_MAGIC_ID_COUNTER 0xdadadada
#define UB_MAGIC_ID_COUNTER 0xbebabeba
#define SPL_START_TEST_OFF 0
#define UB_START_TEST_OFF 58
#define EEPROM_TEST_STRUCT_OFF 116
#define EEPROM_ISEE_BOARD_STRUCT_OFF 121
#define SPL_TEST_COUNTER_OFF 126
#define UB_TEST_COUNTER_OFF 127
#define KNOWN_CRC_CUSTOM_1MB 0x1997c7c7
#define KNOWN_CRC_CUSTOM_1MB_1 0x79f08ba2
#define KNOWN_CRC_CUSTOM_1MB_2 0x177dfc20
#define KNOWN_CRC_CUSTOM_1MB_3 0xa5be2ae0
#define KNOWN_CRC_CUSTOM_1MB_4 0xa8ced8e3
/* CRC PATTERNS FOR RAM TEST */
#define CRC_PATTERN1 0x0000AAAA
#define CRC_PATTERN2 0x00005555
#define CRC_PATTERN3 0x0000CCCC
#define CRC_PATTERN4 0x33330000
#define CRC_PATTERN5 0x99990000
#define CRC_PATTERN6 0x66660000
/* Structs that are involved */
/* SPL / UBOOT RESULT TEST STRUCT */
struct __attribute__((packed)) igep_bootloaders_test {
u16 magic_id; /* SPL or uboot magic id for result of test struct*/
u16 test; /* Results of test */
uint64_t cpuid; /* CPU ID */
u32 crc32; /* CRC32 of the entire struct */
};
/* SPL / UBOOT COUNTER TEST STRUCT */
struct __attribute__((packed)) igep_bootloaders_counter {
u32 magic_id; /* SPL or uboot magic id for counter test struct */
uint64_t count; /* Counter */
u32 crc32; /* CRC32 of the entire struct */
};
/* Functions that are involved */
int test_eeprom(void);
int burn_test(char* t, uint64_t count, int offset);
int burn_test_counter(char* t2, int offset);
int test_counter_check(int offset);
uint64_t test_counter_get(int offset);
int save_test(uint16_t test, uint32_t id, uint64_t cpuid);
uint16_t load_test(uint32_t id);
int erase_eeprom_counter (uint32_t id, int offset);
#endif
if TARGET_AM335X_IGEP0033
config SYS_BOARD
default "igep0033"
config SYS_VENDOR
default "isee"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "am335x_igep0033"
endif
IGEP0033 BOARD
M: Enric Balletbo i Serra <eballetbo@gmail.com>
S: Maintained
F: board/isee/igep0033/
F: include/configs/am335x_igep0033.h
F: configs/am335x_igep0033_defconfig
#
# Makefile
#
# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += mux.o
endif
obj-y += board.o
/*
* Board functions for IGEP COM AQUILA based boards
*
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr3_data = {
.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = K4B2G1646EBIH9_RATIO,
.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
.cmd1csratio = K4B2G1646EBIH9_RATIO,
.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
.cmd2csratio = K4B2G1646EBIH9_RATIO,
.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
.zq_config = K4B2G1646EBIH9_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
};
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr;
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
const struct ctrl_ioregs ioregs = {
.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(400, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
}
#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int rv, ret = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
&cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
ret += rv;
return ret;
}
#endif
/*
* IGEP COM AQUILA boards information header
*
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* We must be able to enable uart0, for initial output. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
#endif
/*
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
/*
* Do board-specific muxes.
*/
void enable_board_pin_mux(void)
{
/* NAND Flash */
configure_module_pin_mux(nand_pin_mux);
/* SD Card */
configure_module_pin_mux(mmc0_pin_mux);
/* Ethernet pinmux. */
configure_module_pin_mux(rmii1_pin_mux);
}
...@@ -3,4 +3,4 @@ M: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com> ...@@ -3,4 +3,4 @@ M: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
S: Maintained S: Maintained
F: board/isee/igep0046/igep0046.c F: board/isee/igep0046/igep0046.c
F: include/configs/igep0046.h F: include/configs/igep0046.h
F: configs/mx6dl_igep0046_2G_defconfig F: configs/mx6dl_igep0046_2G_defconfig
\ No newline at end of file
# #
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> # Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
# #
# (C) Copyright 2011 Freescale Semiconductor, Inc. # Source file for IGEP0046 board
#
# Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
# #
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
obj-y += igep0046_eeprom.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-y += igep0046.o obj-y += igep0046.o
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* EEPROM support source file for IGEP0046 board
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/sys_proto.h>
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
udelay(5000);
}
if(remain > 0){
if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
else
udelay(5000);
}
return 0;
}
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
{
u32 i;
u32 remain = size % 32;
u32 blocks = size / 32;
for (i=0; i < blocks; i++){
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
return -1;
}
}
if(remain > 0)
if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
return -1;
return 0;
}
int check_eeprom (void)
{
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
printf("Could not probe the EEPROM at 0x%x\n",
CONFIG_SYS_I2C_EEPROM_ADDR);
return -1;
}
return 0;
}
unsigned int parse_char(char c)
{
if ('0' <= c && c <= '9') return c - '0';
if ('a' <= c && c <= 'f') return 10 + c - 'a';
if ('A' <= c && c <= 'F') return 10 + c - 'A';
return 0;
}
\ No newline at end of file
/*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
*
* 0046 EEPROM Definitions
*
* Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EEPROM_BOARD_HELPER__
#define __EEPROM_BOARD_HELPER__
int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
int check_eeprom (void);
unsigned int parse_char(char c);
#endif
/* /*
* Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
* *
* Refer docs/README.imxmage for more details about how-to configure * Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image * and create imximage boot image
* *
* The syntax is taken as close as possible with the kwbimage * The syntax is taken as close as possible with the kwbimage
*/ */
/* image version */ /* image version */
IMAGE_VERSION 2 IMAGE_VERSION 2