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MLK-13450-16 fsl_qspi: Update changes for mx7ulp

The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.

Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.

Signed-off-by: Ye Li <ye.li@nxp.com>
imx_v2017.03_4.9.11_1.0.0_ga
Ye Li 4 years ago
parent
commit
5a69ddb7e9
1 changed files with 24 additions and 1 deletions
  1. +24
    -1
      drivers/spi/fsl_qspi.c

+ 24
- 1
drivers/spi/fsl_qspi.c View File

@ -402,6 +402,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
qspi_write32(priv->flags, &regs->mcr, mcr_reg);
}
#ifndef CONFIG_MX7ULP
static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
{
u32 reg, reg2;
@ -424,6 +425,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, &regs->mcr, reg);
}
#endif
/*
* There are two different ways to read out the data from the flash:
@ -446,8 +448,13 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
#ifdef CONFIG_MX7ULP
qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
(0x10 << QSPI_BUF3CR_ADATSZ_SHIFT));
#else
qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
#endif
/* We only use the buffer3 */
qspi_write32(priv->flags, &regs->buf0ind, 0);
@ -461,8 +468,10 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, &regs->bfgencr,
SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
#ifndef CONFIG_MX7ULP
/*Enable DDR Mode*/
qspi_enable_ddr_mode(priv);
#endif
}
#endif
@ -679,7 +688,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
total += 1;
}
#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL)
#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7ULP)
/* iMX7D and MX6UL TXFIFO must be at least 16 bytes*/
for (; total < 4; total++)
qspi_write32(priv->flags, &regs->tbdr, 0);
@ -924,6 +933,18 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
#if defined(CONFIG_MX7ULP)
/*
* mx7ulp QSPI controller does not support parallel mode, it only has port A.
* To support dual die flash and single die flash, we set flash 1 size to CS0 area,
* set flash2 size to CS1 area.
*/
qspi_write32(qspi->priv.flags, &regs->sfa1ad,
FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
qspi_write32(qspi->priv.flags, &regs->sfa2ad,
total_size | amba_bases[bus]);
#else
/*
* Any read access to non-implemented addresses will provide
* undefined results.
@ -942,6 +963,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
total_size | amba_bases[bus]);
qspi_write32(qspi->priv.flags, &regs->sfb2ad,
total_size | amba_bases[bus]);
#endif
qspi_set_lut(&qspi->priv);
@ -1219,6 +1241,7 @@ static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,imx6sx-qspi" },
{ .compatible = "fsl,imx6ul-qspi" },
{ .compatible = "fsl,imx7d-qspi" },
{ .compatible = "fsl,imx7ulp-qspi" },
{ }
};


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