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MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0

The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to
workaround PLL issue.
When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal.

raise: Signal # 8 caught

To avoid such problem, we change our calculation.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f28cf489e1)
imx_v2016.03_4.1.33_7ulp_beta rel_imx_4.1.33_7ulp_beta
Ye Li 3 years ago
parent
commit
43bff39513
1 changed files with 8 additions and 2 deletions
  1. +8
    -2
      arch/arm/cpu/armv7/mx7ulp/scg.c

+ 8
- 2
arch/arm/cpu/armv7/mx7ulp/scg.c View File

@ -500,7 +500,10 @@ u32 decode_pll(enum pll_clocks pll)
infreq = infreq / pre_div;
return infreq * mult + infreq * num / denom;
if (denom)
return infreq * mult + infreq * num / denom;
else
return infreq * mult;
case PLL_A7_APLL:
reg = readl(&scg1_regs->apllcsr);
@ -529,7 +532,10 @@ u32 decode_pll(enum pll_clocks pll)
infreq = infreq / pre_div;
return infreq * mult + infreq * num / denom;
if (denom)
return infreq * mult + infreq * num / denom;
else
return infreq * mult;
case PLL_USB:
reg = readl(&scg1_regs->upllcsr);


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