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MA-9409-3 Add base board support for android and android things.

* add board support for android and android things.
  mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
  reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
  it will be included by android and android things.
  defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
  it's a common code.
* add invalidate_dcache_range in fixed order.
  It will have salt invalid issue if we do not add it in order
* add display for pico-7d.

Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
imx_v2017.03_4.9.11_1.0.0_ga
zhang sanshan 4 years ago
committed by Chen Guoyin
parent
commit
2c1196079e
84 changed files with 6461 additions and 445 deletions
  1. +21
    -1
      arch/arm/cpu/armv7/mx6/Kconfig
  2. +7
    -0
      arch/arm/cpu/armv7/mx7/Kconfig
  3. +23
    -23
      arch/arm/include/asm/arch-mx7/crm_regs.h
  4. +15
    -0
      board/freescale/mx6ul_aquila/Kconfig
  5. +12
    -0
      board/freescale/mx6ul_aquila/Makefile
  6. +120
    -0
      board/freescale/mx6ul_aquila/imximage.cfg
  7. +893
    -0
      board/freescale/mx6ul_aquila/mx6ul_aquila.c
  8. +365
    -0
      board/freescale/mx6ul_aquila/plugin.S
  9. +15
    -0
      board/freescale/mx6ul_nxpu_iopb/Kconfig
  10. +6
    -0
      board/freescale/mx6ul_nxpu_iopb/MAINTAINERS
  11. +10
    -0
      board/freescale/mx6ul_nxpu_iopb/Makefile
  12. +187
    -0
      board/freescale/mx6ul_nxpu_iopb/imximage.cfg
  13. +572
    -0
      board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c
  14. +138
    -0
      board/freescale/mx6ul_nxpu_iopb/plugin.S
  15. +1
    -39
      board/freescale/mx7ulp_evk/mx7ulp_evk.c
  16. +15
    -0
      board/freescale/pico-imx7d/Kconfig
  17. +6
    -0
      board/freescale/pico-imx7d/MAINTAINERS
  18. +10
    -0
      board/freescale/pico-imx7d/Makefile
  19. +116
    -0
      board/freescale/pico-imx7d/imximage.cfg
  20. +160
    -0
      board/freescale/pico-imx7d/imximage_512mb.cfg
  21. +683
    -0
      board/freescale/pico-imx7d/pico-imx7d.c
  22. +227
    -0
      board/freescale/pico-imx7d/plugin.S
  23. +12
    -0
      board/freescale/picosom-imx6ul/Kconfig
  24. +6
    -0
      board/freescale/picosom-imx6ul/MAINTAINERS
  25. +7
    -0
      board/freescale/picosom-imx6ul/Makefile
  26. +114
    -0
      board/freescale/picosom-imx6ul/imximage.cfg
  27. +689
    -0
      board/freescale/picosom-imx6ul/picosom-imx6ul.c
  28. +0
    -1
      common/image-android.c
  29. +1
    -2
      configs/mx6dlsabreautoandroid_defconfig
  30. +1
    -2
      configs/mx6dlsabreautoandroid_nand_defconfig
  31. +1
    -2
      configs/mx6dlsabresdandroid_defconfig
  32. +1
    -2
      configs/mx6qpsabreautoandroid_defconfig
  33. +1
    -2
      configs/mx6qpsabreautoandroid_nand_defconfig
  34. +1
    -2
      configs/mx6qpsabresdandroid_defconfig
  35. +1
    -2
      configs/mx6qsabreautoandroid_defconfig
  36. +1
    -2
      configs/mx6qsabreautoandroid_nand_defconfig
  37. +1
    -2
      configs/mx6qsabresdandroid_defconfig
  38. +1
    -2
      configs/mx6slevkandroid_defconfig
  39. +1
    -2
      configs/mx6sxsabreautoandroid_defconfig
  40. +1
    -2
      configs/mx6sxsabreautoandroid_nand_defconfig
  41. +1
    -2
      configs/mx6sxsabresdandroid_defconfig
  42. +1
    -2
      configs/mx6ul_14x14_evk_android_defconfig
  43. +5
    -0
      configs/mx6ul_14x14_evk_brillo_defconfig
  44. +32
    -0
      configs/mx6ul_aquila_defconfig
  45. +30
    -0
      configs/mx6ul_nxpu_iopb_defconfig
  46. +1
    -2
      configs/mx7dsabresdandroid_defconfig
  47. +8
    -0
      configs/mx7dsabresdbrillo_defconfig
  48. +1
    -2
      configs/mx7ulp_evk_android_defconfig
  49. +2
    -1
      configs/pico-imx6ul_defconfig
  50. +34
    -0
      configs/pico-imx7d_defconfig
  51. +33
    -0
      configs/picosom-imx6ul_defconfig
  52. +13
    -0
      drivers/crypto/fsl_caam.c
  53. +34
    -20
      drivers/usb/gadget/f_fastboot.c
  54. +1
    -7
      drivers/usb/gadget/fastboot_lock_unlock.c
  55. +1
    -1
      include/configs/mx6sabre_common.h
  56. +3
    -50
      include/configs/mx6sabreandroid_common.h
  57. +1
    -1
      include/configs/mx6slevk.h
  58. +2
    -42
      include/configs/mx6slevkandroid.h
  59. +1
    -1
      include/configs/mx6sxsabreauto.h
  60. +2
    -44
      include/configs/mx6sxsabreautoandroid.h
  61. +1
    -1
      include/configs/mx6sxsabresd.h
  62. +2
    -42
      include/configs/mx6sxsabresdandroid.h
  63. +4
    -1
      include/configs/mx6ul_14x14_evk.h
  64. +1
    -43
      include/configs/mx6ul_14x14_evk_android.h
  65. +41
    -0
      include/configs/mx6ul_14x14_evkandroidthings.h
  66. +368
    -0
      include/configs/mx6ul_aquila.h
  67. +41
    -0
      include/configs/mx6ul_aquila_android_things.h
  68. +368
    -0
      include/configs/mx6ul_nxpu_iopb.h
  69. +40
    -0
      include/configs/mx6ul_nxpu_iopb_android_things.h
  70. +3
    -1
      include/configs/mx7dsabresd.h
  71. +55
    -0
      include/configs/mx7dsabresd_androidthings.h
  72. +1
    -44
      include/configs/mx7dsabresdandroid.h
  73. +1
    -1
      include/configs/mx7ulp_evk.h
  74. +1
    -39
      include/configs/mx7ulp_evk_android.h
  75. +56
    -0
      include/configs/mx_android_common.h
  76. +5
    -1
      include/configs/pico-imx6ul.h
  77. +401
    -0
      include/configs/pico-imx7d.h
  78. +57
    -0
      include/configs/pico-imx7dandroidthings.h
  79. +286
    -0
      include/configs/picosom-imx6ul.h
  80. +42
    -0
      include/configs/picosom-imx6ul_android_things.h
  81. +7
    -0
      include/fsl_fastboot.h
  82. +14
    -9
      lib/avb/fsl/utils.c
  83. +6
    -0
      lib/avb/fsl/utils.h
  84. +12
    -0
      scripts/config_whitelist.txt

+ 21
- 1
arch/arm/cpu/armv7/mx6/Kconfig View File

@ -290,6 +290,12 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6UL_NXPU_IOPB
bool "Support mx6ul_nxpu_iopb"
select MX6UL
select DM
select DM_THERMAL
config TARGET_MX6UL_14X14_DDR3_ARM2
bool "mx6ul_14x14_ddr3_arm2"
select BOARD_LATE_INIT
@ -337,6 +343,18 @@ config TARGET_MX6ULL_9X9_EVK
select DM
select DM_THERMAL
config TARGET_PICOSOM_IMX6UL
bool "Support picosom-imx6ul"
select MX6UL
select DM
select DM_THERMAL
config TARGET_MX6UL_AQUILA
bool "Support mx6ul_aquila"
select MX6UL
select DM
select DM_THERMAL
config TARGET_NITROGEN6X
bool "nitrogen6x"
@ -475,6 +493,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6sx_17x17_arm2/Kconfig"
source "board/freescale/mx6sx_19x19_arm2/Kconfig"
source "board/freescale/mx6ul_nxpu_iopb/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
@ -488,7 +507,8 @@ source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/freescale/picosom-imx6ul/Kconfig"
source "board/freescale/mx6ul_aquila/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/apalis_imx6/Kconfig"


+ 7
- 0
arch/arm/cpu/armv7/mx7/Kconfig View File

@ -30,6 +30,12 @@ config TARGET_MX7D_12X12_LPDDR3_ARM2
select DM
select DM_THERMAL
config TARGET_PICO_IMX7D
bool "Support pico-imx7d"
select MX7D
select DM
select DM_THERMAL
config TARGET_MX7D_12X12_DDR3_ARM2
bool "Support mx7d_12x12_ddr3_arm2"
select BOARD_LATE_INIT
@ -82,6 +88,7 @@ source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
source "board/freescale/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"


+ 23
- 23
arch/arm/include/asm/arch-mx7/crm_regs.h View File

@ -2008,29 +2008,29 @@ struct mxc_ccm_anatop_reg {
#define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET 0
#define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET)
#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i))
#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i))
#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i))
#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i))
#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
#define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
#define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
#define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
#define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
#define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
#define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i))
#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))


+ 15
- 0
board/freescale/mx6ul_aquila/Kconfig View File

@ -0,0 +1,15 @@
if TARGET_MX6UL_AQUILA
config SYS_BOARD
default "mx6ul_aquila"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "mx6ul_aquila"
endif

+ 12
- 0
board/freescale/mx6ul_aquila/Makefile View File

@ -0,0 +1,12 @@
# (C) Copyright 2017 Murata Electronics
# (C) Copyright 2015 Freescale Semiconductor, Inc.
# (C) Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6ul_aquila.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@

+ 120
- 0
board/freescale/mx6ul_aquila/imximage.cfg View File

@ -0,0 +1,120 @@
/*
* Copyright (C) 2017 Murata Electronics.
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ul-som-evk/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* New DDR type MT41K256M16TW-107 */
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x000C0030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x415C015C
DATA 4 0x021B0848 0x40404244
DATA 4 0x021B0850 0x40405A58
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00921012
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB66D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000004F
DATA 4 0x021B0000 0x84180000
DATA 4 0x021B0890 0x00400000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
#endif

+ 893
- 0
board/freescale/mx6ul_aquila/mx6ul_aquila.c View File

@ -0,0 +1,893 @@
/*
* Copyright (C) 2017 Murata Electronics
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Specified for EVK consisting of Murata Aquila (iMX6UL + PMIC + eMMC + WiFi/BT) + iMX6UL-Base board
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <linux/sizes.h>
#include <linux/fb.h>
#include <miiphy.h>
#include <mmc.h>
#include <mxsfb.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#ifdef CONFIG_POWER
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#else
#error "Not defined: CONFIG_POWER"
#endif
#ifdef CONFIG_FSL_FASTBOOT
#include <fsl_fastboot.h>
#ifdef CONFIG_ANDROID_RECOVERY
#include <recovery.h>
#endif
#endif /*CONFIG_FSL_FASTBOOT*/
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define IOX_SDI IMX_GPIO_NR(5, 10)
#define IOX_STCP IMX_GPIO_NR(5, 7)
#define IOX_SHCP IMX_GPIO_NR(5, 11)
#define IOX_OE IMX_GPIO_NR(5, 8)
static iomux_v3_cfg_t const iox_pads[] = {
/* IOX_SDI */
MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* IOX_SHCP */
MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* IOX_STCP */
MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* IOX_nOE */
MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
/*
* HDMI_nRST --> Q0
* ENET1_nRST --> Q1
* ENET2_nRST --> Q2
* CAN1_2_STBY --> Q3
* BT_nPWD --> Q4
* CSI_RST --> Q5
* CSI_PWDN --> Q6
* LCD_nPWREN --> Q7
*/
enum qn {
HDMI_nRST,
ENET1_nRST,
ENET2_nRST,
CAN1_2_STBY,
BT_nPWD,
CSI_RST,
CSI_PWDN,
LCD_nPWREN,
};
enum qn_func {
qn_reset,
qn_enable,
qn_disable,
};
enum qn_level {
qn_low = 0,
qn_high = 1,
};
static enum qn_level seq[3][2] = {
{0, 1}, {1, 1}, {0, 0}
};
static enum qn_func qn_output[8] = {
qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, qn_disable,
qn_enable
};
void iox74lv_init(void)
{
int i;
gpio_direction_output(IOX_OE, 0);
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
gpio_direction_output(IOX_OE, 1);
};
void iox74lv_set(int index)
{
int i;
gpio_direction_output(IOX_OE, 0);
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
if (i == index)
gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
else
gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
gpio_direction_output(IOX_OE, 1);
};
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC and EEPROM */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
.gp = IMX_GPIO_NR(1, 28),
},
.sda = {
.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
.gp = IMX_GPIO_NR(1, 29),
},
};
#else
/* Murata Aquila uses PMIC */
#error "Need to define CONFIG_SYS_I2C_MXC"
#endif
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* Murata Aquila does not use VSELECT, CD and RST_B for WiFi control */
};
/* Murata Aquila uses 8-bit eMMC at uSDHC2 */
static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/*
* RST_B
*/
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_SYS_USE_NAND
/* Murata Aquila uses NAND pads for eMMC at uSDHC2 */
#error "Cannot define CONFIG_SYS_USE_NAND"
#endif
#ifdef CONFIG_FEC_MXC
/*
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
* be used for ENET1 or ENET2, cannot be used for both.
*/
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
{
if (fec_id == 0)
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_QSPI
#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
int board_qspi_init(void)
{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
/* Set the clock */
enable_qspi_clk(0);
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
{USDHC2_BASE_ADDR, 0, 8},
};
/* Murata Aquila eMMC reset */
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
int mmc_get_env_devno(void)
{
u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
int dev_no;
u32 bootsel;
bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
/* If not boot from sd/mmc, use default value */
if (bootsel != 1)
return CONFIG_SYS_MMC_ENV_DEV;
/* BOOT_CFG2[3] and BOOT_CFG2[4] */
dev_no = (soc_sbmr & 0x00001800) >> 11;
/* Murata Aquila always use uSDHC2 for eMMC. Note the 1 difference in mapping. */
if (dev_no == 2 && mx6_esdhc_fused(USDHC2_BASE_ADDR))
{
dev_no = 1;
}
return dev_no;
}
int mmc_map_to_kernel_blk(int dev_no)
{
/* Murata Aquila always use uSDHC2 for eMMC and uSDHC1 for WiFi. Note the 1 difference in mapping. */
if (dev_no == 1 && mx6_esdhc_fused(USDHC2_BASE_ADDR))
{
dev_no = 2;
}
return dev_no;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
/* Murata Aquila always has WiFi connected to uSDHC1 which is not available for storage*/
ret = 0;
break;
case USDHC2_BASE_ADDR:
/* Murata Aquila always has eMMC connected to uSDHC2 */
ret = 1;
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1 --> WiFi
* mmc1 USDHC2 --> eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
}
}
return 0;
}
int check_mmc_autodetect(void)
{
char *autodetect_str = getenv("mmcautodetect");
if ((autodetect_str != NULL) &&
(strcmp(autodetect_str, "yes") == 0)) {
return 1;
}
return 0;
}
void board_late_mmc_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_devno();
if (!check_mmc_autodetect())
return;
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#else
#error "Not defined: CONFIG_FSL_ESDHC"
#endif
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
/* LCD_RST */
MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
/*
* Use GPIO for Brightness adjustment, duty cycle = period.
*/
MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct lcd_panel_info_t {
unsigned int lcdif_base_addr;
int depth;
void (*enable)(struct lcd_panel_info_t const *dev);
struct fb_videomode mode;
};
void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
{
enable_lcdif_clock(dev->lcdif_base_addr, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Reset the LCD */
gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
/* Set Brightness to high */
gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
}
static struct lcd_panel_info_t const displays[] = {{
.lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR,
.depth = 24,
.enable = do_enable_parallel_lcd,
.mode = {
.name = "TFT43AB",
.xres = 480,
.yres = 272,
.pixclock = 108695,
.left_margin = 8,
.right_margin = 4,
.upper_margin = 2,
.lower_margin = 4,
.hsync_len = 41,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
displays[i].lcdif_base_addr);
if (!ret) {
if (displays[i].enable)
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
return -EINVAL;
}
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
int ret;
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
return 0;
}
static int setup_fec(int fec_id)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
int ret;
if (0 == fec_id) {
if (check_module_fused(MX6_MODULE_ENET1))
return -1;
/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
if (check_module_fused(MX6_MODULE_ENET2))
return -1;
/* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
}
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};
/* At default the 3v3 enables the MIC2026 for VBUS power */
static void setup_usb(void)
{
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
static struct pmic *pfuze;
int power_init_board(void)
{
int ret;
unsigned int reg, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
return ret;
pfuze = pmic_get("PFUZE3000");
ret = pmic_probe(pfuze);
if (ret)
return ret;
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
reg |= 0x1;
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
/* SW1B step ramp up time from 2us to 4us/25mV */
reg = 0x40;
pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
/* SW1B mode to APS/PFM */
reg = 0xc;
pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
/* SW1B standby voltage set to 0.975V */
reg = 0xb;
pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
return 0;
}
#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
u32 vddarm;
struct pmic *p = pfuze;
if (!p) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.275V */
pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
value &= ~0x1f;
value |= PFUZE3000_SW1AB_SETP(1275);
pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
set_anatop_bypass(1);
vddarm = PFUZE3000_SW1AB_SETP(1175);
pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
value &= ~0x1f;
value |= vddarm;
pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
#endif
#endif
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
iox74lv_init();
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
#ifdef CONFIG_FEC_MXC
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_init();
#endif
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
return 0;
}
u32 get_board_rev(void)
{
return get_cpu_rev();
}
int checkboard(void)
{
puts("Board: Murata MX6UL-Aquila\n");
return 0;
}
#ifdef CONFIG_ANDROID_RECOVERY
int is_recovery_key_pressing(void)
{
/* No key defined for this board */
return 0;
}
#endif

+ 365
- 0
board/freescale/mx6ul_aquila/plugin.S View File

@ -0,0 +1,365 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* DDR script */
.macro imx6ul_ddr3_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x000C0000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
ldr r1, =0x00000030
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
ldr r1, =0x00000030
str r1, [r0, #0x260]
str r1, [r0, #0x264]
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00000030
str r1, [r0, #0x280]
ldr r1, =0x00000030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00000000
str r1, [r0, #0x80C]
ldr r1, =0x41570155
str r1, [r0, #0x83C]
ldr r1, =0x4040474A
str r1, [r0, #0x848]
ldr r1, =0x40405550
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x00921012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x0002002D
str r1, [r0, #0x004]
ldr r1, =0x1B333030
str r1, [r0, #0x008]
ldr r1, =0x676B52F3
str r1, [r0, #0x00C]
ldr r1, =0xB66D0B63
str r1, [r0, #0x010]
ldr r1, =0x01FF00DB
str r1, [r0, #0x014]
ldr r1, =0x00201740
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x000026D2
str r1, [r0, #0x02C]
ldr r1, =0x006B1023
str r1, [r0, #0x030]
ldr r1, =0x0000004F
str r1, [r0, #0x040]
ldr r1, =0x84180000
str r1, [r0, #0x000]
ldr r1, =0x23400A38
str r1, [r0, #0x890]
ldr r1, =0x02008032
str r1, [r0, #0x01C]
ldr r1, =0x00008033
str r1, [r0, #0x01C]
ldr r1, =0x00048031
str r1, [r0, #0x01C]
ldr r1, =0x15208030
str r1, [r0, #0x01C]
ldr r1, =0x04008040
str r1, [r0, #0x01C]
ldr r1, =0x00000800
str r1, [r0, #0x020]
ldr r1, =0x00000227
str r1, [r0, #0x818]
ldr r1, =0x0002552D
str r1, [r0, #0x004]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6ul_ddr3_eol_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x000C0000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
ldr r1, =0x00000030
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
ldr r1, =0x00000030
str r1, [r0, #0x260]
str r1, [r0, #0x264]
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00000030
str r1, [r0, #0x280]
ldr r1, =0x00000030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00000000
str r1, [r0, #0x80C]
ldr r1, =0x41490145
str r1, [r0, #0x83C]
ldr r1, =0x40404546
str r1, [r0, #0x848]
ldr r1, =0x4040524D
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x00921012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x0002002D
str r1, [r0, #0x004]
ldr r1, =0x00333030
str r1, [r0, #0x008]
ldr r1, =0x676B52F3
str r1, [r0, #0x00C]
ldr r1, =0xB66D8B63
str r1, [r0, #0x010]
ldr r1, =0x01FF00DB
str r1, [r0, #0x014]
ldr r1, =0x00201740
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x000026D2
str r1, [r0, #0x02C]
ldr r1, =0x006B1023
str r1, [r0, #0x030]
ldr r1, =0x0000004F
str r1, [r0, #0x040]
ldr r1, =0x84180000
str r1, [r0, #0x000]
ldr r1, =0x02008032
str r1, [r0, #0x01C]
ldr r1, =0x00008033
str r1, [r0, #0x01C]
ldr r1, =0x00048031
str r1, [r0, #0x01C]
ldr r1, =0x15208030
str r1, [r0, #0x01C]
ldr r1, =0x04008040
str r1, [r0, #0x01C]
ldr r1, =0x00000800
str r1, [r0, #0x020]
ldr r1, =0x00000227
str r1, [r0, #0x818]
ldr r1, =0x0002552D
str r1, [r0, #0x004]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6ul_lpddr2_evk_setting
ldr r0, =IOMUXC_BASE_ADDR
ldr r1, =0x00080000
str r1, [r0, #0x4B4]
ldr r1, =0x00000000
str r1, [r0, #0x4AC]
ldr r1, =0x00000030
str r1, [r0, #0x27C]
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
str r1, [r0, #0x288]
ldr r1, =0x00000000
str r1, [r0, #0x270]
str r1, [r0, #0x260]
str r1, [r0, #0x264]
ldr r1, =0x00000030
str r1, [r0, #0x4A0]
ldr r1, =0x00020000
str r1, [r0, #0x494]
ldr r1, =0x00003030
str r1, [r0, #0x280]
ldr r1, =0x00003030
str r1, [r0, #0x284]
ldr r1, =0x00020000
str r1, [r0, #0x4B0]
ldr r1, =0x00000030
str r1, [r0, #0x498]
str r1, [r0, #0x4A4]
str r1, [r0, #0x244]
str r1, [r0, #0x248]
ldr r0, =MMDC_P0_BASE_ADDR
ldr r1, =0x00008000
str r1, [r0, #0x1C]
ldr r1, =0x1b4700c7
str r1, [r0, #0x85c]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x00470000
str r1, [r0, #0x890]
ldr r1, =0x00000800
str r1, [r0, #0x8b8]
ldr r1, =0x33333333
str r1, [r0, #0x81C]
str r1, [r0, #0x820]
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
ldr r1, =0x20000000
str r1, [r0, #0x83C]
ldr r1, =0x4040484F
str r1, [r0, #0x848]
ldr r1, =0x40405247
str r1, [r0, #0x850]
ldr r1, =0x00922012
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
ldr r1, =0x00020012
str r1, [r0, #0x004]
ldr r1, =0x00000000
str r1, [r0, #0x008]
ldr r1, =0x33374133
str r1, [r0, #0x00C]
ldr r1, =0x00100A82
str r1, [r0, #0x010]
ldr r1, =0x00170557
str r1, [r0, #0x038]
ldr r1, =0x00000093
str r1, [r0, #0x014]
ldr r1, =0x00001748
str r1, [r0, #0x018]
ldr r1, =0x00008000
str r1, [r0, #0x01C]
ldr r1, =0x0F9F0682
str r1, [r0, #0x02C]
ldr r1, =0x009F0010
str r1, [r0, #0x030]
ldr r1, =0x00000047
str r1, [r0, #0x040]
ldr r1, =0x83100000
str r1, [r0, #0x000]
ldr r1, =0x003F8030
str r1, [r0, #0x01C]
ldr r1, =0xFF0A8030
str r1, [r0, #0x01C]
ldr r1, =0x82018030
str r1, [r0, #0x01C]
ldr r1, =0x04028030
str r1, [r0, #0x01C]
ldr r1, =0x01038030
str r1, [r0, #0x01C]
ldr r1, =0x00001800
str r1, [r0, #0x020]
ldr r1, =0x00000000
str r1, [r0, #0x818]
ldr r1, =0xA1310003
str r1, [r0, #0x800]
ldr r1, =0x00025576
str r1, [r0, #0x004]
ldr r1, =0x00010106
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x01C]
.endm
.macro imx6_clock_gating
ldr r0, =CCM_BASE_ADDR
ldr r1, =0xFFFFFFFF
str r1, [r0, #0x68]
str r1, [r0, #0x6C]
str r1, [r0, #0x70]
str r1, [r0, #0x74]
str r1, [r0, #0x78]
str r1, [r0, #0x7C]
str r1, [r0, #0x80]
.endm
.macro imx6_qos_setting
.endm
.macro imx6_ddr_setting
#if defined (CONFIG_MX6UL_9X9_LPDDR2)
imx6ul_lpddr2_evk_setting
#elif defined(CONFIG_DDR3L_MT41K256M16HA)
imx6ul_ddr3_eol_evk_setting
#else
imx6ul_ddr3_evk_setting
#endif
.endm
/* include the common plugin code here */
#include <asm/arch/mx6_plugin.S>

+ 15
- 0
board/freescale/mx6ul_nxpu_iopb/Kconfig View File

@ -0,0 +1,15 @@
if TARGET_MX6UL_NXPU_IOPB
config SYS_BOARD
default "mx6ul_nxpu_iopb"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "mx6ul_nxpu_iopb"
endif

+ 6
- 0
board/freescale/mx6ul_nxpu_iopb/MAINTAINERS View File

@ -0,0 +1,6 @@
MX6ULIOPB BOARD
M: Fang Hui <hui.fang@nxp.com>
S: Maintained
F: board/freescale/mx6ul_nxpu_iopb/
F: include/configs/mx6ul_nxpu_iopb.h
F: configs/mx6ul_nxpu_iopb_defconfig

+ 10
- 0
board/freescale/mx6ul_nxpu_iopb/Makefile View File

@ -0,0 +1,10 @@
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6ul_nxpu_iopb.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@

+ 187
- 0
board/freescale/mx6ul_nxpu_iopb/imximage.cfg View File

@ -0,0 +1,187 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM nor
#else
BOOT_FROM sd
#endif
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifdef CONFIG_DDR3L_MT41K256M16HA
/* DDR type MT41K256M16HA-125 which is EOL */
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x00000030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x41490145
DATA 4 0x021B0848 0x40404546
DATA 4 0x021B0850 0x4040524D
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333