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MLK-16333 imx8qm/qxp: Change memory region 0x0-0x1c000000 to strongly order

This memory region is for LSIO subsystem, including OCRAM, AP ROM,
flexspi0 mapped memory and flexspi1 buffer. If we set it to cachable,
the AHB read in flexspi driver will have coherence problem.

This patch set this memory region to strongly order to avoid any issue
in driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 1ffcff6a1e)
Ye Li 3 years ago
parent
commit
18ab60d4fd
1 changed files with 1 additions and 2 deletions
  1. +1
    -2
      arch/arm/cpu/armv8/imx8/cpu.c

+ 1
- 2
arch/arm/cpu/armv8/imx8/cpu.c View File

@ -992,8 +992,7 @@ void dram_init_banksize(void)
static u64 get_block_attrs(sc_faddr_t addr_start)
{
if ((addr_start >= PHYS_SDRAM_1 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
|| (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))
|| (addr_start >= 0x0 && addr_start <= ((sc_faddr_t)0x20000000)))
|| (addr_start >= PHYS_SDRAM_2 && addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
return (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN);


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