Browse Source

mpc8xx: remove RPXlite_dw, quantum board support

These boards are old enough and have no maintainers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
imx_3.14.38_6ul_engr
Masahiro Yamada 6 years ago
committed by Tom Rini
parent
commit
0657e46e28
28 changed files with 3 additions and 2765 deletions
  1. +0
    -5
      arch/powerpc/cpu/mpc8xx/cpu_init.c
  2. +0
    -4
      arch/powerpc/cpu/mpc8xx/scc.c
  3. +0
    -5
      arch/powerpc/cpu/mpc8xx/serial.c
  4. +0
    -8
      board/RPXlite_dw/Makefile
  5. +0
    -161
      board/RPXlite_dw/README
  6. +0
    -164
      board/RPXlite_dw/RPXlite_dw.c
  7. +0
    -474
      board/RPXlite_dw/flash.c
  8. +0
    -82
      board/RPXlite_dw/u-boot.lds
  9. +0
    -121
      board/RPXlite_dw/u-boot.lds.debug
  10. +0
    -8
      board/quantum/Makefile
  11. +0
    -247
      board/quantum/fpga.c
  12. +0
    -16
      board/quantum/fpga.h
  13. +0
    -243
      board/quantum/quantum.c
  14. +0
    -82
      board/quantum/u-boot.lds
  15. +0
    -114
      board/quantum/u-boot.lds.debug
  16. +0
    -9
      boards.cfg
  17. +2
    -0
      doc/README.scrapyard
  18. +0
    -1
      drivers/pcmcia/Makefile
  19. +0
    -10
      drivers/pcmcia/mpc8xx_pcmcia.c
  20. +0
    -73
      drivers/pcmcia/rpx_pcmcia.c
  21. +0
    -5
      drivers/video/mpc8xx_lcd.c
  22. +0
    -2
      include/common.h
  23. +0
    -26
      include/commproc.h
  24. +0
    -462
      include/configs/RPXlite_DW.h
  25. +0
    -430
      include/configs/quantum.h
  26. +1
    -4
      include/pcmcia.h
  27. +0
    -4
      post/cpu/mpc8xx/ether.c
  28. +0
    -5
      post/cpu/mpc8xx/uart.c

+ 0
- 5
arch/powerpc/cpu/mpc8xx/cpu_init.c View File

@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
@ -206,10 +205,6 @@ void cpu_init_f (volatile immap_t * immr)
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
rpxlite_init ();
#endif
#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;


+ 0
- 4
arch/powerpc/cpu/mpc8xx/scc.c View File

@ -461,10 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
#ifdef CONFIG_RPXLITE
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;


+ 0
- 5
arch/powerpc/cpu/mpc8xx/serial.c View File

@ -182,11 +182,6 @@ static int smc_init (void)
#endif
#endif /* CONFIG_FADS */
#if defined(CONFIG_RPXLITE)
/* Enable Monitor Port Transceiver */
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
#endif /* CONFIG_RPXLITE */
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/


+ 0
- 8
board/RPXlite_dw/Makefile View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = RPXlite_dw.o flash.o

+ 0
- 161
board/RPXlite_dw/README View File

@ -1,161 +0,0 @@
After following the step of Yoo. Jonghoon and Wolfgang Denk,
I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW.
Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH
RPXlite RPXlite CW 850 16MB 4MB
RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB
This fireware is specially coded for EmbeddedPlanet Co. Software Development
Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
It has the following three features:
1. 64MHz/48MHz system frequence setting options.
The default setting is 48MHz.To get a 64MHz u-boot,just add
'64' in make command,like
make distclean
make RPXlite_DW_64_config
make all
2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM
The default environment parameter is stored in FLASH because it is a common choice for
environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
home.Because of the possibility of using two firewares on this board,I didn't
'disturb' EEPROM.To get NVRAM support,you may use the following build command:
make distclean
make RPXlite_DW_NVRAM_config
make all
3. LCD panel support
To support the Platform better,I added LCD panel(NL6448BC20-08) function.
For the convenience of debug, CONFIG_PERBOOT was supported. So you just
perss ENTER if you want to get a serial console in boot downcounting.
Then you can switch to LCD and serial console freely just typing
'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
To get a LCD support u-boot,you can do the following:
make distclean
make RPXlite_DW_LCD_config
make all
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The basic make commands could be:
make RPXlite_DW_config
make RPXlite_DW_64_config
make RPXlite_DW_LCD_config
make RPXlite_DW_NVRAM_config
BTW,you can combine the above features together and get a workable u-boot to meet your need.
For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
make RPXlite_DW_NVRAM_64_LCD_config
make all
So other combining make commands could be:
make RPXlite_DW_NVRAM_64_config
make RPXlite_DW_NVRAM_LCD_config
make RPXlite_DW_64_LCD_config
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The boot process by "make RPXlite_DW_config" could be:
U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
Board: RPXlite_DW
DRAM: 64 MB
FLASH: 16 MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: SCC ETHERNET
u-boot>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
A word on the U-Boot environment variable setting and usage :
In the beginning, you could just need very simple default environment variable setting,
like[include/configs/RPXlite.h] :
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
This is enough for kernel NFS test. But as debug process goes on, you would expect
to save some time on environment variable setting and u-boot/kernel updating.
So the default environment variable setting would become more complicated. Just like
the one I did in include/configs/RPXlite_DW.h.
Two u-boot commands, ku and uu, should be careful to use. They were designed to update
kernel and u-boot image file respectively. You must tftp your image to default address
'100000' and then use them correctly. Yeah, you can create your own command to do this
job. :-) The example u-boot image updating process could be :
u-boot>t 100000 RPXlite_DW_LCD.bin
Using SCC ETHERNET device
TFTP from server 172.16.115.6; our IP address is 172.16.115.7
Filename 'RPXlite_DW_LCD.bin'.
Load address: 0x100000
Loading: #############################
done
Bytes transferred = 144700 (2353c hex)
u-boot>run uu
Un-Protect Flash Sectors 0-4 in Bank # 1
Erase Flash Sectors 0-4 in Bank # 1
.... done
Copy to Flash... done
ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2
ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 -
ff000020: 31353a32 303a3238 29000000 00000000 15:20:28).......
ff000030: 00000000 00000000 00000000 00000000 ................
ff000040: 00000000 00000000 00000000 00000000 ................
ff000050: 00000000 00000000 00000000 00000000 ................
ff000060: 00000000 00000000 00000000 00000000 ................
ff000070: 00000000 00000000 00000000 00000000 ................
ff000080: 00000000 00000000 00000000 00000000 ................
ff000090: 00000000 00000000 00000000 00000000 ................
ff0000a0: 00000000 00000000 00000000 00000000 ................
ff0000b0: 00000000 00000000 00000000 00000000 ................
ff0000c0: 00000000 00000000 00000000 00000000 ................
ff0000d0: 00000000 00000000 00000000 00000000 ................
ff0000e0: 00000000 00000000 00000000 00000000 ................
ff0000f0: 00000000 00000000 00000000 00000000 ................
u-boot updating finished
u-boot>
Also for environment updating, 'run eu' could let you erase OLD default environment variable
and then use the working u-boot environment setting.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Finally, if you want to keep the serial port to possible debug on spot for deployment, you
just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string
defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot.
I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
I would particually thank Wolfgang Denk for his nice help.
Enjoy,
Sam Song, samsongshu@yahoo.com.cn
Institute of Electrical Machinery and Controls
Shanghai University
Oct. 11, 2004

+ 0
- 164
board/RPXlite_dw/RPXlite_dw.c View File

@ -1,164 +0,0 @@
/*
* (C) Copyright 2004
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Sam Song
* U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
* Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
* with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
*/
#include <common.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
0x01FFCC20, 0x1FF74C20, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
_NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
0x01FFFC24, 0x1FF74C25, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
*/
0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
/* INIT sequence RAM WORDS
* SDRAM Initialization (offset 0x36 in UPMA RAM)
* The above definition uses the remaining space
* to establish an initialization sequence,
* which is executed by a RUN command.
* The sequence is COMMAND INHIBIT(NOP),Precharge,
* Load Mode Register,NOP,Auto Refresh.
*/
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
};
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: RPXlite_DW\n") ;
return (0) ;
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
memctl->memc_mar = 0x00000088;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
/*Disable Periodic timer A. */
udelay(200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
/*Enable Periodic timer A */
udelay (1000);
/* Check Bank 0 Memory Size
* try 9 column mode
*/
size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
/*
* Final mapping:
*/
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
udelay (1000);
return (size9);
}
void rpxlite_init (void)
{
/* Enable NVRAM */
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
return (get_ram_size (base, maxsize));
}

+ 0
- 474
board/RPXlite_dw/flash.c View File

@ -1,474 +0,0 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
* U-Boot port on RPXlite board
*
* Some of flash control words are modified. (from 2x16bit device
* to 4x8bit device)
* RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
* are not tested.
*
* (?) Does an RPXLite board which
* does not use AM29LV800 flash memory exist ?
* I don't know...
*/
/* Yes,Yoo.They do use other FLASH for the board.
*
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
* U-Boot port on RPXlite DW version board
*
* By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
* The total FLASH has 16MB(4x4MB).
* I just made some necessary changes on the basis of Wolfgang and Yoo's job.
*
* June 8, 2004 */
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions vu_long : volatile unsigned long IN include/common.h
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
unsigned long flash_init (void)
{
unsigned long size_b0 ;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* If Monitor is in the cope of FLASH,then
* protect this area by default in case for
* other occupation. [SAM] */
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
return (size_b0);
}
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if (info->flash_id & FLASH_BTYPE) {
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000);
}
} else {
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00010000;
info->start[i--] = base + info->size - 0x00018000;
info->start[i--] = base + info->size - 0x00020000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00040000;
}
}
}
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
break;
/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
addr[0xAAA] = 0x00AA00AA ;
addr[0x555] = 0x00550055 ;
addr[0xAAA] = 0x00900090 ;
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[2] ; /* device ID */
switch (value & 0x00FF00FF) {
case (AMD_ID_LV400T & 0x00FF00FF):
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV400B & 0x00FF00FF):
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV800T & 0x00FF00FF):
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV800B & 0x00FF00FF):
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00400000; /* Size doubled by yooth */
break; /* => 4 MB */
case (AMD_ID_LV160T & 0x00FF00FF):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV160B & 0x00FF00FF):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_DL323B & 0x00FF00FF):
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000;
break; /* => 16 MB(4x4MB) */
/* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013
* AMD_ID_DL323B could be found in <flash.h>.[SAM]
* So we could get : flash_id = 0x00000013.
* The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (info->flash_id & FLASH_BTYPE) {
/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
* it means bottom boot flash. GOOD IDEA! [SAM]
*/
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x00010000;
info->start[3] = base + 0x00018000;
info->start[4] = base + 0x00020000;
info->start[5] = base + 0x00028000;
info->start[6] = base + 0x00030000;
info->start[7] = base + 0x00038000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + ((i-7) * 0x00040000) ;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00010000;
info->start[i--] = base + info->size - 0x00018000;
info->start[i--] = base + info->size - 0x00020000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00040000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
/* info->protect[i] = addr[4] & 1 ; */
/* Mask it for disorder FLASH protection **[Sam]** */
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *)info->start[0];
*addr = 0xF0F0F0F0; /* reset bank */
}
return (info->size);
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0x80808080;
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long *)(info->start[sect]) ;
addr[0] = 0x30303030 ;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_long *)info->start[0];
addr[0] = 0xF0F0F0F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long *)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0xAAA] = 0xAAAAAAAA;
addr[0x555] = 0x55555555;
addr[0xAAA] = 0xA0A0A0A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

+ 0
- 82
board/RPXlite_dw/u-boot.lds View File

@ -1,82 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

+ 0
- 121
board/RPXlite_dw/u-boot.lds.debug View File

@ -1,121 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

+ 0
- 8
board/quantum/Makefile View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = quantum.o fpga.o

+ 0
- 247
board/quantum/fpga.c View File

@ -1,247 +0,0 @@
/*
* (C) Copyright 2001-2003
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* The DEBUG define must be before common to enable debugging */
#undef DEBUG
#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include "fpga.h"
/* ------------------------------------------------------------------------- */
#define MAX_ONES 226
/* MPC850 port D */
#define PD(bit) (1 << (15 - (bit)))
# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */
# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */
# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */
# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */
# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */
/* DDR 0 - input, 1 - output */
#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */
#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data)
#define GET_FPGA immr->im_ioport.iop_pddat
#define FPGA_WRITE_1 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
int fpga_boot (unsigned char *fpgadata, int size)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int i, index, len;
int count;
#ifdef CONFIG_SYS_FPGA_SPARTAN2
int j;
unsigned char data;
#else
unsigned char b;
int bit;
#endif
debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
/* display infos on fpgaimage */
printf ("FPGA:");
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf (" %s", &(fpgadata[index + 1]));
index += len + 3;
}
printf ("\n");
index = 0;
#ifdef CONFIG_SYS_FPGA_SPARTAN2
/* search for preamble 0xFFFFFFFF */
while (1) {
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
&& (fpgadata[index + 2] == 0xff)
&& (fpgadata[index + 3] == 0xff))
break; /* preamble found */
else
index++;
}
#else
/* search for preamble 0xFF2X */
for (index = 0; index < size - 1; index++) {
if ((fpgadata[index] == 0xff)
&& ((fpgadata[index + 1] & 0xf0) == 0x30))
break;
}
index += 2;
#endif
debug ("FPGA: configdata starts at position 0x%x\n", index);
debug ("FPGA: length of fpga-data %d\n", size - index);
/*
* Setup port pins for fpga programming
*/
immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/*
* Init fpga by asserting and deasserting PROGRAM*
*/
SET_FPGA (FPGA_CLK | FPGA_DATA);
/* Wait for FPGA init line low */
count = 0;
while (GET_FPGA & FPGA_INIT) {
udelay (1000); /* wait 1ms */
/* Check for timeout - 100us max, so use 3ms */
if (count++ > 3) {
debug ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_LOW;
}
}
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/* deassert PROGRAM* */
SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
/* Wait for FPGA end of init period . */
count = 0;
while (!(GET_FPGA & FPGA_INIT)) {
udelay (1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3) {
debug ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_HIGH;
}
}
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
debug ("write configuration data into fpga\n");
/* write configuration-data into fpga... */
#ifdef CONFIG_SYS_FPGA_SPARTAN2
/*
* Load uncompressed image into fpga
*/
for (i = index; i < size; i++) {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if ((i % 1024) == 0)
printf ("%6d out of %6d\r", i, size); /* let them know we are alive */
#endif
data = fpgadata[i];
for (j = 0; j < 8; j++) {
if ((data & 0x80) == 0x80) {
FPGA_WRITE_1;
} else {
FPGA_WRITE_0;
}
data <<= 1;
}
}
/* add some 0xff to the end of the file */
for (i = 0; i < 8; i++) {
data = 0xff;
for (j = 0; j < 8; j++) {
if ((data & 0x80) == 0x80) {
FPGA_WRITE_1;
} else {
FPGA_WRITE_0;
}
data <<= 1;
}
}
#else
/* send 0xff 0x20 */
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
/*
** Bit_DeCompression
** Code 1 .. maxOnes : n '1's followed by '0'
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
** 255 : '1'
*/
for (i = index; i < size; i++) {
b = fpgadata[i];
if ((b >= 1) && (b <= MAX_ONES)) {
for (bit = 0; bit < b; bit++) {
FPGA_WRITE_1;
}
FPGA_WRITE_0;
} else if (b == (MAX_ONES + 1)) {
for (bit = 1; bit < b; bit++) {
FPGA_WRITE_1;
}
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
FPGA_WRITE_0;
}
FPGA_WRITE_1;
} else if (b == 255) {
FPGA_WRITE_1;
}
}
#endif
debug ("\n\n");
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
/*
* Check if fpga's DONE signal - correctly booted ?
*/
/* Wait for FPGA end of programming period . */
count = 0;
while (!(GET_FPGA & FPGA_DONE)) {
udelay (1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3) {
debug ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_DONE;
}
}
debug ("FPGA: Booting successful!\n");
return 0;
}

+ 0
- 16
board/quantum/fpga.h View File

@ -1,16 +0,0 @@
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Virtex2 FPGA configuration support for the QUANTUM computer
*/
int fpga_boot(unsigned char *fpgadata, int size);
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */

+ 0
- 243
board/quantum/quantum.c View File

@ -1,243 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
#include "fpga.h"
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
unsigned long flash_init (void);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] = {
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18h in UPMA RAM)
*/
0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh. (Offset 30h in UPMA RAM)
* (Initialization code at 0x36)
*/
0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
/*
* Exception. (Offset 3Ch in UPMA RAM)
*/
0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
char buf[64];
int i;
int l = getenv_f("serial#", buf, sizeof(buf));
puts ("Board QUANTUM, Serial No: ");
for (i = 0; i < l; ++i) {
if (buf[i] == ' ')
break;
putc (buf[i]);
}
putc ('\n');
return (0); /* success */
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size9;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_mar = 0x00000088;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/* Check Bank 0 Memory Size,
* 9 column mode
*/
size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
/*
* Final mapping:
*/
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
udelay (1000);
return (size9);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile ulong *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)(base + cnt); /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *)(base + cnt); /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long);
cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
}
/*
* Miscellaneous intialization
*/
int misc_init_r (void)
{
char *fpga_data_str = getenv ("fpgadata");
char *fpga_size_str = getenv ("fpgasize");
void *fpga_data;
int fpga_size;
int status;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
int flash_size;
/* Remap FLASH according to real size */
flash_size = flash_init ();
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
if (fpga_data_str && fpga_size_str) {
fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
status = fpga_boot (fpga_data, fpga_size);
if (status != 0) {
printf ("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf ("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
}
}
return 0;
}

+ 0
- 82
board/quantum/u-boot.lds View File

@ -1,82 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

+ 0
- 114
board/quantum/u-boot.lds.debug View File

@ -1,114 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }