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MLK-11028 imx: mx6qp change L2 prefetch offset to 0

Change L2 prefetch offset to 0 to make system stable.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 5cab58016a)
imx_v2014.04_3.14.38_6qp_beta
Peng Fan 5 years ago
parent
commit
2bc93d766d
1 changed files with 1 additions and 1 deletions
  1. +1
    -1
      arch/arm/cpu/armv7/mx6/soc.c

+ 1
- 1
arch/arm/cpu/armv7/mx6/soc.c View File

@ -1075,7 +1075,7 @@ void v7_outer_cache_enable(void)
/* Turn on the L2 I/D prefetch, double linefill */
/* Set prefetch offset with any value except 23 as per errata 765569 */
val |= 0x7000000f;
val |= 0x70000000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0


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